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2/11/06 12:44 AM
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jgibson
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Edited: 11-Feb-06
Member Since: 04/30/2001
Posts: 6055
 
My digital systems prof finds it amusing to give either 0 or 1 points on assignments that take hours to complete. For example, I spent quite a bit of time designing a state machine with 8 states. On one of my output eqns I put a Q instead of a Q' in the product term. I earned a big fat 0. FAWK!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2/11/06 10:16 AM
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signaljammer
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Edited: 11-Feb-06
Member Since: 06/25/2003
Posts: 1109
what an asshat... Isn't your school on a 4.0 scale? Tell him he would need 5 bits for that.... What did your state machine do? I like to coding for microprocessors but I'm starting to learn vhdl on my own... which is making me a bit more familiar with state machines.
2/11/06 1:37 PM
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jgibson
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Edited: 11-Feb-06
Member Since: 04/30/2001
Posts: 6058
Do you prefer VHDL to Verilog? I like Verilog because it's syntax is much closer to C, the language I cut my teeth on.

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